Frequency synthesizers utilizing a phase lock loop (PLL) to provide an output signal having a selectable, precise and stable frequency are well known in the art. Typically, a PLL includes a tunable oscillator such as voltage controlled oscillator (VCO), the output of which is locked to a known reference signal by means of a phase comparator. The phase comparator generates an output voltage or current that is proportional to the phase difference between the known reference signal and the VCO output signal. The output of the phase comparator is coupled back to the input of the VCO to tune and lock the VCO to a desired frequency. This forces the VCO output to have the same frequency as the reference signal.
To provide a frequency synthesizer having a variable output frequency, a divider circuit is interposed between the output of the VCO and the phase comparator, wherein the VCO output frequency is divided by a selectable divisor before it is compared with the reference frequency. The VCO output frequency will then be an exact multiple of the referenced frequency. If the divisor, N, is an integer, the smallest increment in the VCO output frequency value is necessarily equal to the magnitude of the reference frequency itself. Thus, in order to provide a frequency synthesizer having a small step size between adjacent output frequencies, a very low reference frequency is required. However use a very low reference frequency introduces unacceptable effects such as limited frequency range and a long settling time for the PLL.
A technique known as fractional-N synthesis is often utilized to synthesize output signals having a frequency which is a rational multiple of the reference signal frequency. Typically, frequency divider circuits are implemented in such a manner that they only divide by an integer value. It is thus necessary to simulate fractional division by changing the divisor integer value temporarily during the course of a division cycle. The noninteger division ratios are realized by dividing by N+1, for example, instead of N on a proportional number of division cycles to provide an average division ratio which approximates the desired rational divisor number. For example, if the desired rational divisor is taken to be N.1, the divide value will be N for nine division cycles and N+1 for the tenth division cycle. Thus, when averaged over ten cycles the division factor equals N.1 and the VCO output frequency will be N.1 times the reference frequency. Such a fractional-N technique is disclosed in U.S. Pat. No. 3,928,813 issued to Charles A. Kingsford Smith on Dec. 23, 1975.
While such fractional-N dividers are widely used for frequency synthesis, switching between different divisor values results in undesirable phase error or phase "jitter" near the desired carrier frequency. When switching between adjacent integer divide ratios, the average divide ratio is correct, but the instantaneous divide ratio is never correct, which results in phase error at the phase detector output. This phase error phase modulates the VCO to generate spurious signals collectively known as phase jitter.
One technique for reducing jitter in a fractional-N synthesizer is disclosed in U.S. Pat. No. 5,038,117, entitled "Multiple Modulator Fractional-N Divider," issued to the inventor of the present invention on Aug. 5, 1991, the disclosure of which is incorporated herein by reference. In accordance with that technique, jitter is reduced by employing in the frequency synthesizer a multiple modulator fractional-N divider which comprises a programmable divider and a modulus control circuit. The programmable divider operates to divide the frequency output signal of the frequency synthesizer by an integer modulus value to form an intermediate frequency signal which will be compared to the reference frequency signal by the frequency synthesizer's phase comparator.
The modulus control circuit comprises a first modulator and one or more additional sigma-delta modulators arranged in cascade fashion. The circuit receives as inputs an integer divisor value and a fractional divisor value corresponding to the desired rational divisor and provides the integer modulus value to the programmable divider. A summation circuit forms the integer modulus value as the weighted sum of all the modulator outputs. The first sigma-delta modulator, which can be implemented as an accumulator, accumulates the fractional divisor value. When the accumulator overflows, the first modulator overflow signal changes to a value of one for a single clock cycle, resulting in a corresponding increase to the integer modulus value. This varies the modulus of the programmable divider on a proportional number of division cycles to provide an average division ratio equal to the desired rational divisor number as described above.
The additional sigma-delta modulators are connected in cascade fashion to the first modulator and act to reduce the jitter associated with the fractional N division technique. Each modulator subsequent to the first acts to track out the error of the modulator that precedes it. The conditioned sum of these modulators is summed with the output signal of the first modulator to form the integer modulus value. This added modulation of the integer modulus value acts to reduce the phase jitter or fractional spurs associated with fractional-N synthesis.
Each of the additional modulators has as its input the error signal of the preceding modulator (represented by the contents of the accumulator) and accumulates the preceding modulator's error signal every clock cycle. These accumulations periodically overflow, generating an overflow signal which is taken as the output signal of the sigma-delta modulator. Each overflow signal is coupled via a summer to a differentiator circuit. For each overflow signal generated by a modulator, the differentiator generates a positive pulse and then a negative pulse in the next clock cycle. The output of the differentiator is coupled to the summer associated with the preceding sigma-delta modulator. The thus conditioned sum of the additional modulators produces a zero mean signal which acts to diminish the error present in the first modulator.
The above described multiple modulator based frequency synthesis technique is effective for reducing phase jitter associated with fractional-N synthesis (fractional spurs). However, the technique is only effective if the modulators are sufficiently random. Certain fractional divisor values, 1/2 and 1/4 for example, do not induce sufficient randomness. Instead a deterministic pattern of short length is produced that results in undesirable spurs in the frequency spectrum of the synthesized signal. These spurs are known as structure spurs because they are created by a lack of randomness or over-abundance of structure in the modulator's idle pattern.
Consider, for example, a three modulator fractional-N divider where 1/2 is used as the fractional divisor value. Table 1 below shows the values accumulated in the integrators of the three modulators assuming an initial accumulated value of zero in each integrator. Notice that a pattern forms which repeats every four clock cycles. As a result, when the modulator is used in a frequency synthesizer under these conditions, structure spurs will be created at frequencies of 1/4 and 1/2 of the frequency synthesizer's reference frequency.
TABLE 1 ______________________________________ Ref. Accum Ovfl Accum Ovfl Accum Ovfl Cycle 1 1 2 2 3 3 ______________________________________ 0 0 0 0 0 0 0 1 .5 0 .5 0 .5 0 2 0 1 .5 0 0 1 3 .5 0 0 1 0 0 4 0 1 0 0 0 0 5 .5 0 .5 0 .5 0 . . . . . . . . . . . . . . ______________________________________
Structure spurs can be dealt with in several ways. First, one could simply avoid frequency synthesis of frequencies that have excessive structure spurs. However, avoiding synthesis of certain frequencies can be done only at the expense of system flexibility. A second option would be to seed the integrators with starting values that tend to randomize modulator operation at the expense of arbitrary phase control. A third possibility is that of narrowing the bandwidth of the frequency synthesizer's phase locked-loop to filter all objectionable structure spurs. This last option, however, is done at the expense of switching speed and phase noise.
The present invention provides a simple method for reducing structure spurs. In accordance with the present invention, two or more numbers (addends) are alternately added to the fractional divisor value before it is input to the multiple modulator fractional-N divider. For example, in a particular embodiment of the invention, the numbers 0 and 2 are alternately added to the fractional divisor value. This causes the limit cycle of the cascaded modulators to have maximum length, thus destroying the short term periodicity associated with certain fractional divisor values which create structure spurs.
If the means of the alternating addends is not zero, the fractional divisor value will be offset. In the embodiment described above where the addends are 0 and 2, the fractional divisor value will be offset by 1. If such an offset exists, it is necessary to also subtract the offset from the fractional divisor value before it is input to the multiple modulator fractional-N divider.
Underflow and overflow of the fractional divisor value when the addend is added and the offset subtracted must also be accommodated. Overflow can be accommodated by incrementing the integer divisor value by one. Underflow can be accommodated by decrementing the integer divisor value by one.
Implementation of the structure spur reduction technique is simple. A summer circuit connected in series with the fractional divisor value input of the multiple modulator fractional-N divider can be used to perform the addition of alternate addends. Alternating selection of the addends can be performed by a switch connected to the summer. A second summer circuit connected in series with the fractional divisor value input can perform the subtraction of the offset. Incrementing and decrementing of the integer divisor value to accommodate offsets can be performed by a third summer circuit connected in series with the integer divisor input.
Additional features and advantages of the present invention will be made apparent from the following detailed description of a preferred embodiment, which proceeds with reference to the accompanying drawings.